Impedance matching means that when energy is transmitted, the load impedance must be equal to the characteristic impedance of the transmission line. At this time, there is no reflection in the transmission, which indicates that all energy is absorbed by the load. On the contrary, there is energy loss in transmission. In high-speed PCB design, the matching of impedance is related to the quality of the signal.
It does not mainly look at the frequency, but the key is to look at the steepness of the signal edge, that is, the rise / fall time of the signal. It is generally considered that if the rise / fall time of the signal (in terms of 10% to 90%) is less than 6 times the wire delay, it is high speed Signal, we must pay attention to the problem of impedance matching. The wire delay is generally set to 150ps / inch.
During the propagation of a signal along a transmission line, if there is a consistent signal propagation speed everywhere on the transmission line, and the capacitance per unit length is the same, then the signal always sees a completely consistent instantaneous impedance during the propagation process. Since the impedance remains constant throughout the transmission line, we give a specific name to indicate this characteristic or characteristic of a specific transmission line, and call it the characteristic impedance of the transmission line. The characteristic impedance refers to the instantaneous impedance value when the signal is seen along the transmission line. The characteristic impedance is related to the board layer on which the PCB conductors are located, the material (dielectric constant) used by the PCB, the trace width, and the distance between the conductor and the plane, and has nothing to do with the trace length. The characteristic impedance can be calculated using software. In high-speed PCB wiring, the trace impedance of digital signals is generally designed to be 50 ohms, which is an approximate number. Generally, the coaxial cable baseband is 50 ohms, the frequency band is 75 ohms, and the twisted pair (differential) is 100 ohms.
Under the condition that the impedance of the signal source is lower than the characteristic impedance of the transmission line, a resistor R is connected in series between the signal source and the transmission line, so that the output impedance of the source matches the characteristic impedance of the transmission line, and the signal reflected from the load is suppressed. A second reflection occurred.
Matching resistance selection principle: The sum of the matching resistance value and the output impedance of the driver is equal to the characteristic impedance of the transmission line. The output impedance of common CMOS and TTL drivers will change with the level of the signal. Therefore, for a TTL or CMOS circuit, it is impossible to have a very correct matching resistor, only a compromise can be considered. Signal networks with a chain topology are not suitable for series termination. All loads must be connected to the end of the transmission line.
Tandem matching is the most commonly used terminal matching method. Its advantages are low power consumption, no additional DC load to the driver, no additional impedance between the signal and ground, and only a resistive element is needed.
Common applications: impedance matching for general CMOS and TTL circuits. USB signals are also sampled this way for impedance matching.
In the case where the impedance at the signal source is very small, the input impedance at the load end can be matched with the characteristic impedance of the transmission line by increasing the parallel resistance to eliminate the reflection at the load end. Implementation forms are divided into two forms of single resistance and double resistance.
Matching resistance selection principle: When the chip's input impedance is very high, for the single resistance type, the parallel resistance value at the load end must be similar to or equal to the characteristic impedance of the transmission line; for the dual resistance type, each parallel resistance value It is twice the characteristic impedance of the transmission line.
The advantages of parallel terminal matching are simple and easy, and the obvious disadvantage is that it will bring DC power consumption: the DC power consumption of the single resistance method is closely related to the duty cycle of the signal; the dual resistance method no matter whether the signal is high or low All have DC power dissipation, but the current is half less than the single resistance method.
Common applications: There are many applications with high-speed signals.
(1) SSTL driver such as DDR, DDR2. It adopts a single resistance form and is connected in parallel to VTT (generally half of IOVDD). The DDR2 data signal's parallel matching resistor is built into the chip.
(2) High-speed serial data interface such as TMDS. It adopts single-resistor form, and it is connected to IOVDD in parallel at the receiving device. The single-ended impedance is 50 ohms (100 ohms between differential pairs).
